The present invention relates to a technique of semiconductor devices, and particularly to a technique which is applicable effectively to the layout of power lines of semiconductor devices.
A semiconductor device including logic circuits, for example, has a fundamental structure of laying internal circuits in the middle of a semiconductor chip (substrate), laying multiple input/output circuit cells to surround the internal circuits, and laying external terminals for the input/output circuit cells. In this structure, multiple power lines having a shape of planar rings (will be termed “ring power lines” hereinafter) running around the outer edge of the internal circuits are laid between the internal circuits and the external terminals thereby to conduct power voltages to the internal circuits and input/output circuit cells. Power conduction to the ring power lines is from the external terminals for power supply.
The inventors of the present invention have studied a technique, in which the external terminals and ring power lines are formed of a same wiring layer. For the connection of an external terminal for power supply to a ring power line which is located inner than the outmost ring power line, the external power supply terminal cannot be connected directly (as a unitary stuff) to the inner ring power line due to the layout of at least the outmost ring power line between the terminal and the inner line, and therefore the external terminal for power supply needs to be connected to the inner ring power line through another wiring layer via thru-holes.
A power line layout technique is disclosed in Japanese Unexamined Patent Publication No. 2000-311964 for example, in which power pads 12 are formed of a wiring layer separately from the wiring layer of power lines, i.e., equivalent to the ring power lines mentioned above, and these members are connected electrically through electrical contacts.